1. Field of the Invention
The present invention relates to a field effect transistor.
2. Description of the Related Art
Conventionally, there has been known a field effect transistor (FET) in which a semiconductor substrate has an active layer, a source region and a drain region at an upper portion thereof. The active layer is located between the source and the drain regions. A gate electrode is provided on the active layer. A source electrode is in ohmic contact with the source region. A drain electrode is in ohmic contact with the drain region.
When the FET is in operation, an electric field is concentrated at an edge of the drain region opposed to the gate electrode (i.e. a boundary portion between the drain region and the active layer), causing a high voltage to be applied to the boundary portion. This may result in a leakage of an electric current at the boundary portion and/or a dielectric breakdown. Therefore, the transistor is difficult to be used in high voltage.
Another type of FET is known in which the active layer has a recess on which the gate electrode is provided. When the transistor is in operation, an electric field is concentrated at a corner of the recess. As a result, the transistor is difficult to be used in high voltage.
As related art, Japanese Patent Publication No. 6-338610 discloses a MOS type field effect transistor in which a gate oxide film is provided between the gate electrode and the semiconductor substrate and is extended to a region between the drain electrode and a boundary between the drain region and the drift region.